52031BR

CHINA - Wuhan

Job Description and Requirements :
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon IP business is all about integrating more capabilities into an So C—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
ASIC Digital Design Manager
Seeking a highly motivated and innovative digital design manager with extensive knowledge of ASIC development flow. The candidate would be leading a highly experienced mixed-signal design team, targeting the current and next generation USB4.0, PCIe4.0, Ethernet, DP2.0, HDMI2.1, and MIPI MPHY products (up to 24 Gbps). Strong theoretical and practical background in high-speed serializer and data recovery circuits is a strong plus. The position offers an excellent opportunity to work with an expert team of digital, mixed-signal and system engineers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on prototype test-chips.

The PHY IP development is very dynamic and provides an endless list of challenges. The candidate would be guided by a strong leadership team comprised of top experts in the field as well as provided continuous on the job training and assignments. The work is very challenging, not only given the constant technological changes but also given the vast responsibilities and the need to charter unknown waters.

Key Qualifications

• MSEE plus a minimum of 10 years of digital design and verification experience in the industry
• Good experience in assessing product requirements and micro-architecting a great hardware design.
• Must have deep knowledge of ASIC digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows
• Good theoretical and practical understanding of digital signal processing and data recovery circuits is required
• Good communication skills for interacting between different design groups and customer support teams are required
• Must be self-motivated, proactive, and able to balance good design quality while meeting tight deadlines
• Resolves issues and manages conflict in creative ways and exercises independent judgment in selecting methods and techniques to obtain solutions
• Networks with senior internal and external personnel in own area of expertise to grow the team.
• Must exhibit ability to produce high quality results as a technical leader.

Preferred Experience

• Manage a team of local digital design engineers responsible for SERDES hard and soft RTL IP development.
• Interface with the Application Engineering team, Digital Place and Route team, Analog design team, and Technical Marketing teams.
• Act as a technical lead for the design projects. Review standards specifications, prepare micro-architecture specifications, provide guidelines and review RTL implementation, synthesis constraints, CDC constraints and waivers, ATPG, and ATE vector generation.
• Conduct performance reviews of team members and provide constructive and accurate feedback to the team members.
• Should have experience in defining synthesis design constraints and resolving STA issues.
• Should have expertise in clock/Reset domain crossing design reviews and evaluating viol

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Engineering

China

ASIC Digital Design

Employee