• Lead implementation and drive u ARCH optimization of Si Five’s high performance Out of Order RISC-V CPU's from RTL to GDSII
• Close ambitious performance, power, and area (PPA) goals at block and/or CPU subsystem level
• Collaborate closely with the microarchitecture and RTL teams to identify and optimize PPA trade offs, also includes path finding for next generation of CPUs
• Create timing and area models for configurability for predictable execution
• Contribute to physical implementation flow development and Foundation IP (standard cell, SRAM) improvement to drive best-in-class automation and PPA

• 12+ years of physical implementation experience with multiple tape outs in a wide range of technologies; Experience with CPU implementation and advanced process nodes (3nm and below) is strongly preferred;
• Well versed with Synopsys/Cadence Silicon Implementation tools
• Expertise in aggressive PPA optimization through physical design techniques
• Working knowledge for out of order core u Arch and logic design is strongly preferred
• Prior experience in leading/managing teams is preferred
• Attention to detail and a focus on high-quality design
• Ability to work well with others and a belief that engineering is a team sport
• Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

India