Overview: Responsibilities: THE ROLE:
The AMD NBIO Team is on the lookout for a dynamic, upbeat IP Validation Design Engineer to join our growing team. As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.


THE PERSON:

• Must have excellent written and verbal communication skills.
• Must excel in a dynamic team working environment.
• Leadership and mentoring skills a definite asset.
• Must be a self-starter and be able to independently drive tasks to completion.

KEY RESPONSIBILITIES:
As an IP Validation Design Engineer, you will drive the planning, validation, and debug of various hardware IP for forthcoming AMD APU, CPU, Compute and Discrete Graphics SOC programs.
Responsibilities include:

• Defining, documenting, executing and reporting the overall functional test plan and validation strategy for a set of AMD IP’s.
• Driving technical innovation to enhance AMD's capabilities in IP validation, including tools and scripts/automation development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives.
• Debugging IP issues found during pre-silicon, bring-up, system validation, and production phases of the SOC programs.
• Engaging on pre-silicon ‘shift left’ activities with cross-functional teams including but not limited to Design Verification (DV), Diagnostics, FPGA-based Emulation and other software/hardware modeling frameworks to ensure readiness for first silicon arrival, enablement of IP functionality, and debug of critical features.
• Leading collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives.
• Developing knowledge of system architecture/debug and other internal IP’s.
• Supporting issues on customer platforms as requested by customer support teams.

PREFERRED EXPERIENCE:

• Experience in digital logic design/verification/post-silicon validation.
• Extensive experience with ASIC debug techniques and methodologies.
• Extensive knowledge of physical and protocol levels of common high-speed interfaces an asset.
• Extensive experience with board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization.
• Strong scripting skills (eg. Ruby, Python).
• Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.
• In-depth knowledge of PC architectures/PCIe protocol.
• Must have excellent written and verbal communication skills.
• Must excel in a dynamic team working environment.
• Leadership and mentoring skills a definite asset.
• Must be a self-starter and be able to independently drive tasks to completion.

ACADEMIC CREDENTIALS:

• Bachelor’s or master’s degree majoring in EE, CS or related field.
  

LOCATION:
Penang, Malaysia


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