51745BR

ROMANIA - Bucharest

Seeking a Senior VLSI frontend Leader to lead a team of IP design/ verification activities for Solutions Group at the Bucharest development center, Romania. This challenging senior role combines technical expertise with leadership responsibilities in a multi-site environment, focusing on developing IP Cores for connectivity protocols in the Design and Verification domains.

Job Responsibilities

This requires a dynamic individual to lead a talented team in defining and envisioning innovative features for our products. This role requires deftly switching between managing the team and making significant technical contributions. Responsibilities extend to hiring, planning, ensuring quality, tracking execution to plan, risk management and mitigation. In addition to interacting with customers, the ideal candidate must be well-versed in ASIC design methodologies, verification strategies, and must possess the ability to interact with upper management confidently. This is an opportunity to thrive in a project and team-oriented global environment. In addition, managing individuals including performance reviews, calibrating individuals, team growth and development, mentoring and managing career growth of the team is part of the overall responsibility.

Growing the team in Bucharest, Romania is a key requirement of the role.

Key Qualifications

• Ideally should have 15+ years of relevant industrial experience including at least 10 years as an individual contributor in VSLI designs.
• Strong people management background with proven skills in leading large teams, setting up technical processes, customer interactions, project planning and tracking, managing deliveries, and working with remote teams.
• Familiarity with protocols such as, high speed serial protocols PCIe/CXL/UCIe, Memory Protocols, AMBA.
• Hands-on experience in creating complex designs - Proficiency in Verilog/System Verilog coding and Simulation tools along with knowledge of synthesis flow, static timing flows, formal checking, and experience with Perforce or a similar revision control environment. Exposure to quality processes in the context of IP design and verification is considered an added advantage.
• Experience in Verification: UVM/VMM/OVM/e RM-based verification methodologies - Proficiency in creating test benches for complex designs, utilizing constrained random verification methods, test planning, and coverage management - Familiarity with optimizing simulation runs, utilizing AI-based tools for failure categorization, and exposure to revision control environments like Perforce - Exposure to quality processes for IP design and verification is a plus.
• Strong interpersonal skills, demonstrating the ability to effectively influence and collaborate with individuals at all levels within the organization and excellent problem-solving ability.
• Additionally, they should exhibit excellent written and verbal communication abilities, be adept at conflict resolution, and maintain composure in high-pressure situations.
• A positive team player with a "Yes, If" attitude and a willingness to work within constraints is essential.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Engineering

Romania

R&D Engineering

Employee