• Analyze product yield limiters, drive failures on Automatic Test Equipment (ATE) at wafer and package level
• Characterize different aspects of performance and power to take competitive products to market
• Lead multi-functional efforts with design, foundry, quality, test, customers and suppliers to root-cause problems and implement improvements
• Identify and implement test processes to improve manufacturing efficiency.
• Influence future ASIC designs to improve test coverage and enable better product yield, test time, silicon bring-up and releases

• Bachelor's degree in Electrical Engineering (or equivalent experience) and 2+ years of relevant experience
• Structured data-driven problem solving and critical thinking
• Proficiency in data analysis using Python or JMP
• Working knowledge of digital/analog circuits and device physics
• Experience with test coverage, PVTF silicon characterization and AEC-Q100 qualification is preferred but not required

The base salary range is 104,000 USD - 201,250 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.