Must Have

• Bachelor's or Master's degree or Ph D in Electrical Engineering, Computer Engineering, or a related field
• Solid understanding of digital design fundamentals, including RTL coding (VHDL or Verilog)
• Experience in FPGA or ASIC design flow, including synthesis, place and route, and static timing analysis
• Familiarity with FPGA architectures, DSP techniques, and communication protocols (e.g., AXI4)
• Knowledge of verification methodologies and simulation tools
• Excellent problem-solving and debugging skills
• Effective communication and teamwork abilities
  

Nice to Have

• Experience in developing IP cores for digital communication systems
• Knowledge of Xilinx Zynq Ultra Scale+ MPSo C / RFSo C platforms
• Strong programming skills in C/C++ and scripting languages (e.g., Python, Tcl)
• Language skills in German
• Previous experience in a similar role or relevant internships/projects
  

Responsibilities

• Develop and optimize FPGA/ASIC designs for Creonic's IP cores, considering performance, power, and area constraints
• Conduct RTL coding, synthesis, and verification using industry-standard tools and methodologies
• Perform functional and timing analysis to ensure designs meet specifications
• Collaborate with software engineers
• Support the integration and testing of IP cores on target platforms
• Stay up to date with the latest trends and technologies in FPGA/ASIC design
• Continuous improvement of development processes and methodologies
  

Flexibility

Trainings

Job Bike

Eat & Drink