Germany Job Openings

NXP Semiconductors

Principal Digital Modelling and Design Engineer (f/m/d)

Hamburg

FULL TIME

October 18, 2024

Ready to join the future of innovation in Digital Design Engineering?

This opening is within the Advanced Chip Engineering (ACE) So C Implementation Organization, a central R&D Design group responsible for end-to-end IC/So C implementation of the Automotive and Industrial Automation Processors in NXP.


We are seeking a Principal Digital Modelling and Design Engineer (f/m/d) to join our team in Hamburg, Germany. The Hamburg So C integration team develops complete “System on Chip” products in the domain of Radar applications and Radio Infotainment. International relocation can be accommodated for qualified candidates.

Your Responsibilities:
  • Design, modelling and elaboration of abstractions that enable pre-silicon simulations of HW design using industry CAD tools
  • Creation of HW, IC/IP and So C models using System C that enable early SW prototyping
  • Programming in Matlab/Simulink: Modelling and abstraction of HW IC/IP from architectural concepts and/or requirements
  • FPGA tooling, design and verification: Creation of HW models from early RTL that enable early development
  • Automation using scripting languages like Python or Perl
  • Analysis, comparison and selection of different circuit topologies for optimal design: Ability to generate models and early RTL using CAD tools
  • Contributing to micro-architecture, RTL design and integration of a System on Chip (So C) or So C sub-system, from requirements specification to tape-out and beyond
  • Working with different functions like architecture, verification, DFT, physical implementation, post-silicon validation, etc. to provide early models that enable earlier progress
  • Ability to create models for digital circuits that include the following areas:
    • Digital signal processing IPs: filters, mixers, state machines, etc.
    • Clock and reset infrastructure
    • On-chip interconnect and interfaces
    • ARM CPU/MCU and DSP architectures
    • Design for low power and UPF modelling
    • Communication/control peripherals like PCIe, USB, DDR
    • AMS circuits and IPs including PLLs, receivers, transmitters, LDOs, amplifiers, mixersetc


  • Develop and deliver signed-off verilog RTL and associated deliverables (e.g. clock/reset domain constraints, timing constraints, design documentation)
  • Performance, power, area and timing optimizations of your design following requirements and other constrains established by IC So C Product architects
  • Resolve design problems using knowledge of several of the following areas:
    • Digital signal processing architecture and design
    • Clock and reset infrastructure
    • On-chip interconnect and interfaces
    • ARM CPU/MCU and DSP architectures
    • Design for low power and UPF modelling
    • Communication/control peripherals like PCIe, USB, DDR

Our Team:
As part of the Advanced Chip Engineering R&D team in our company, the product development of a large significant portion of NXP roadmap comes out of this organization and, consequently, there is remarkable visibility to the Corporate NXP Management team.
The candidate would be integrated in a team based in Hamburg, Germany and with day-to-day interactions with other design teams based locally or abroad. Our team has a track record of more than 20 years of successful product designs and innovation.

Your Profile:
  • The candidate should have significant experience with modelling using System C: advanced level is desired
  • Modelling experience using programming in Matlab/Simulink is highly desired
  • Experience with FPGA tooling and design is also a must
  • Proven experience with automation using several programming and scripting languages like Python or Perl
  • Digital IP or So C design engineer with experience in all aspects of RTL design flow i.e. from specification to micro-architecture, RTL design, verification, timing analysis, area/power estimation and DFT concepts
  • The candidate should have a strong experience in RTL design, digital signal processing, So C integration, RTL signoff tools (Synthesis/CDC/RDC/Lint)
  • Basic knowledge of compute core (ARM or RISC-V) / DSP architectures as well as ARM-Amba bus protocols would be considered a plus
  • Fluent written and verbal communication in English


Key Soft Skills:
  • Proficient skills in both written and verbal communication, can articulate well
  • Ability to work in a collaborative and fast-paced dynamic environment
  • Can demonstrate emotional intelligence and ability to work well as a part of local and international teams


Education & Seniority:
  • Degree in Electrical Engineering or Computer Science
  • At least 5 years of experience on IP/Sub-system or So C modelling and digital design

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