Germany Job Openings
NXP Semiconductors
Senior Verification Design Engineer (f/m/d)
Hamburg
FULL TIME
September 2, 2024
We are seeking a senior Verification Design Engineer to join our team in Hamburg, Germany. The Hamburg So C integration team develops complete “System on Chip” products in the domain of Radar applications and Radio Infotainment products.
Your Responsibilities:
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Responsible for defining and writing verification plans based on requirements documents
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Define verification strategy according to design specification documents.
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Responsible for architecting and developing UVM- and SW- based verification environment for RTL simulation.
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Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, Gate level, Emulation platform),
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Run regression, collect and analyze code/functional coverage.
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Provide guidance and support for verification engineers.
Our team
As part of the Microprocessor and Microcontroller R&D team in our company, the product development of a large significant portion of NXP roadmap comes out of this organization and, consequently, there is remarkable visibility to the Corporate NXP Management team.
The candidate would be integrated in a team based in Hamburg, Germany and with day-to-day interactions with other design teams based locally or abroad. Our team has a track record of more than 20 years of successful product designs and innovation.
Your profile
To be successful in this role you must have:
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Proven experience in testbench design and development using UVM methodology for IP/Subsystem/So Cs.
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Proven experience in verification sign-off at IP/Sub System/So C level with test plan development, functional & code coverage analysis
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Proven experience in EDA tools from Cadence (Xcelium, Simvision, Verisium, v Manager, Jasper) and / or Synopsys (VCS, Verdi)
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Understanding of software development for embedded CPUs, and experience in developing and debugging software.
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Basic experience in execution of Gate Level Netlist simulation with back-annotated timing.
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Basic experience on writing System Verilog assertions
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Basic understanding of Formal flow /methodologies
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Ability to question and identify weaknesses in specifications, tool environments, etc.
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Pro-active attituded engineer with proven experience in digital IP & So C verification & good communication skills
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Fluency in English language.
Key Soft Skills
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Proficient skills in both written and verbal communication. Can articulate well.
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Ability to work in a collaborative and fast-paced dynamic environment.
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Can demonstrate emotional intelligence and ability to work well as a part of local and international teams.
Education & seniority
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M.Sc. Degree in Electrical Engineering or Computer Science, with 5+ years of experience on IP/Sub-System/So C Verification
NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
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