Italy Job Openings
Synopsys
Physical Design Engineer, Sr. Staff
Pavia
September 5, 2024
52220BR
ITALY - Pavia
Job Description and Requirements
As an ASIC Physical Implementation, Sr Staff Engineer, the successful candidate will work on a variety of advanced SERDES developments including the latest 56/112/224G standards. The digital implementation organization is seeking a motivated person responsible for the physical implementation of complex IPs and testchips across multiple process technologies with a specific focus on very advanced high speed SERDES platforms.
In this role, you will be responsible for the Physical Implementation of high-speed interface IPs and test-chips, driving all aspects from RTL to GDS including timing and physical sign-off. You will work in close interaction and collaborative teamwork with multiple functional groups (front end digital, analog design and layout, CAD) and the product team.
The successful candidate will have the following: 10 + years of digital or physical design experience with recent contribution to project tape-outs, as a technical driver and/or project head.
Key Qualifications:
Our Silicon IP business is all about integrating more capabilities into an So C—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
In this role, you will be responsible for the Physical Implementation of high-speed interface IPs and test-chips, driving all aspects from RTL to GDS including timing and physical sign-off. You will work in close interaction and collaborative teamwork with multiple functional groups (front end digital, analog design and layout, CAD) and the product team.
The successful candidate will have the following: 10 + years of digital or physical design experience with recent contribution to project tape-outs, as a technical driver and/or project head.
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Intimate understanding of the full design cycle from RTL to GDSII, including chip level.
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Experience with advanced Fin FET nodes, TSMC 16 nanometer or below, including low-power design techniques
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A solid engineering understanding of the underlying concepts of digital design and architecture, implementation flows and physical and timing signoff
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Development of timing constraints and design architectures to ensure on-time delivery, and to meet or exceed power and area targets
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Excellent communication skills, ability to think and communicate at different levels of abstraction, with peer groups as well as customers.
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Methodology guided with excellent software and scripting skills (Perl, Tcl, Python); understanding of CAD automation methods.
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Solid understanding of the challenges inherent in analog/digital interfaces.
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Autonomous, and able to cope with interrupts.
Key Qualifications:
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MSEE and 8+ years or BSEE and 10+ years
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Previous project leadership experience
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Solid understanding of digital / mixed signal verification flows and SOC integration challenges.
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Ability to travel internationally as required.
Our Silicon IP business is all about integrating more capabilities into an So C—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
Job Category
Engineering
Country
Italy
Job Subcategory
ASIC Physical Design
Hire Type
Employee
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