At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our EDAG Business Group (Design Technology) is at the forefront of next-generation semiconductor technology innovation. Working closely with our leading foundry partners and fabless customers, we develop design and EDA technologies for next-generation process technology. In particular, we play a key role in the development of EDA technologies that are essential to enable semiconductor breakthroughs such as Gate-All-Around (GAA) and Backside Power Delivery Network (BSPDN).

We are looking for a talented and enthusiastic new colleague:

R&D Engineer

This job position will closely collaborate with imec Research Center and its partners. Imec is a world-leading R&D and innovation hub for semiconductors and digital technology located in Leuven, Belgium. In this role you would work closely with the engineering teams of IMEC as well as our own teams to enhance collaboration.

You will be a member of the team driving Power-Performance-Area (PPA) optimization at the most advanced process node. You would help to develop methodologies and flow that help new process technology definition and design prototypes using SNPS EDA tools. Also, you would be working very closely with R&D and Foundry partners and should be able to develop novel solutions in the System Technology Co-Optimization space (STCO).

Responsibilities

• STCO and Pathfinding on the next generation of nodes
• Understanding of Multi-Die/3DIC solution and Digital Implementation space to drive STCO solution development.
• Effectively identify design optimization opportunities (silicon, package, EDA, architecture configuration, methodology, etc)

Requirements

• MSc/Ph D degree in Electrical Engineering or Computer Engineering with 1 + years of experience in Digital Design, Physical Design, Place and Route, 3DIC Design/Multi-Die domains
• A strong understanding of Semiconductor Physics would be preferred.
• Experience in using EDA tools like SNPS Fusion Compiler, 3DIC Compiler, Platform Architect.