Job Description and Requirements
As a Staff A&MS Layout Engineer you will collaborate in the development of advanced analog integrated circuit designs using best-in-class Synopsys suite of tools. You will be working with local and global SERDES teams in developing layout for complex analog mixed-signal designs in the latest technology nodes. In your role you will be responsible for taking on top-level block ownership and the creation of highly complex blocks. As a member of our Solutions IP Design Group, you will be developing IP in various technology nodes and foundries for various customers in a fast paced environment.


Responsibilities and Duties

• Leading and managing top-level blocks
• Coordinating with other layout team members for top-level integration as well as designing and reviewing layout designs
• Collaborate with circuit team for feasibility layout of new products
• Optimize layout designs for performance, power, and area
• Work with Rn D Experts to perform layout verification and resolve any design-related customer issues

Qualifications

• BSEE or MSEE with at least 4 years of direct industry experience
• In depth knowledge with layout of analog and mixed signal CMOS circuits
• Proficient with full custom analog layout design tool: Custom Compiler (or equivalent)
• Prior knowledge and proficiency of schematic driven layout editor tools such as Custom Compiler SDL or Virtuoso XL
• Must have a solid working knowledge of DRC, LVS and be able to debug results from ICV tools
• Experience with advanced Fin FET nodes is required
• Ability to use foundry design rule manuals to debug DRC errors is required
• Good written and verbal English skills
• Experience with TCL, SKILL, PERL, Python or other language scripting is a plus
• In-depth experience with regards to:
  • Layout design with consideration for reliability (EMIR/DFM)
  • Layout design to optimize for parasitic layout effects (matching/proximity effects)
  • Layout optimization for signal integrity (clock/data routes, differential routing, shielding)
  • Implementation of ESD design constraints, latch-up risk mitigation
  • Experience with PERC is a plus
• Has excellent communication skills, ability to interact with cross-functional teams
• Experience with the following tools is a plus:
  • Jira/Atlassian
  • ICV Work Bench
  • ICC/ICC2/Fusion Compiler

This position is based in Canada. Candidates must have legal work status in Canada and be able to work in-office in a hybrid work model.


Our Silicon IP business is all about integrating more capabilities into an So C—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.


At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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Should you require an accommodation, please contact hr-help-canada@synopsys.com