Canada Job Openings
Synopsys
Physical Design Methodology Engineer, Sr. Staff
Ottawa
October 15, 2024
We are looking for a R&D Engineer, Staff/Sr Staff to join the Digital Methodology Core Team (MCT). In this position, you will be expected to lead and oversee the integration, and continuous management of methodologies designed by this Core Team into Silicon IP teams. This is a matrix position where leading with influence and trust is highly prized. You will be a successful candidate in this role if you enjoy a breadth of technical understanding with a willingness to drive results while assessing relative risks on quality. This role will require strong verbal and written communication skills.
You are expected to have demonstrated previous experience balancing technical and leadership roles in at least two aspects of ASIC development covering anything from Front-End Development (RTL and Verification) to Back-End Development (PNR). You are also expected to have strong systems-level thinking to judge workflows and processes and make recommendations for improvement. You are an ideal candidate if you have previous specialization in at least two of the following areas but candidates with experience in multiple areas will be highly preferred:
- Lint/CDC
- ATPG/DFT
- Static Timing Analysis and timing budgeting
- Synthesis
- Place and Route
- Physical verification
Key job responsibilities
- Manage and mentor a team of MCT engineers supporting Silicon IP teams by integrating Methodologies into their development infrastructures and showing successful results
- Synthesize goals and milestones from senior leadership and MCT engineers to create plans and roadmaps using MBOs (Management by Objectives)
- Provide quarterly assessment of workflows and results, and make recommendations to the MCT team for improvement
- Hold regular cross-functional meetings to connect the MCT team with the Silicon IP teams, and maintain judicious notes to track status and report completion rates
- Assist in logistical and technical tasks as necessary
- Bachelor's/Master's degree in electrical or computer engineering and computer science
- 10+ years of experience running Front-End and Back-End Synthesis in advanced technology nodes, and using state-of-the-art EDA tools such as DC, ICC2, FC (Fusion Compiler)
- 5+ years of experience writing code in RTL for multi-clock designs, and with a strong understanding of Clock-Domain-Crossing (CDC) principles
- 5+ years of experience driving designs through EDA tools such as Tetra Max, Spy Glass, VC Spy Glass, Z01X, TCM (Fishtail), Prime Power and VCS
- Familiarity with Functional Verification, including understanding of Assertions and Coverage
- Strong experience writing in RTL, TCL, Perl, and/or Python
- Understanding of Machine Learning Concepts and AI
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