Overview: Responsibilities:

• Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications.
• Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS.
• Work with multi-functional teams and handling schedules
• The successful candidate may also be responsible of:

• Debugging and verifying block-/chip-level DFT/DFX features
• Porting or creating the DFT/DFX verification environment.
• Block/chip test plan creation and development.
• Stimulus writing and debug, and regression clean-up.
• Generating high quality manufacturing test patterns for stuck-at, transition fault models and using on-chip test compression techniques
• Simulating and verifying the ATPG and LBIST patterns
• Working with the product engineering teams on the delivery of manufacturing test patterns.

• 5+ years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus.
• Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST
• Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl)
• Familiar with Verilog design language, Verilog simulator and waveform debugging tools
• Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus.
• Strong problem-solving skills.
• Team player with strong communication skills.

• Bachelor’s or Master’s degree in electrical/Electronic Engineering

Qualifications: