Italy Job Openings
Marvell
Analog Layout Intern
Pavia
FULL TIME
September 10, 2024
- Be part of a growing team focused on the layout development and delivery of foundational IP and analog layouts for SOCs and test chips.
- Collaborate with local teams in Italy and global teams in Argentina, Singapore, the U.S., and Europe.
- Gain hands-on experience with various IC layout development and physical verification tools.
- Receive training in mask and layout design using Cadence Virtuoso EXL/Custom Compiler and Synopsys tools based on circuit designs.
- Learn and apply design rules for advanced CMOS technology nodes from 16nm to 3nm.
- Conduct DRC (Design Rule Check) and LVS (Layout Versus Schematic) checks.
- Understand and apply electromagnetic and IR drop (EMIR) concepts in analog IC layout.
- Work on optimizing layout designs for area and parasitics (R, C).
- Work closely with your team and collaborate effectively with colleagues to achieve successful outcomes.
- Currently enrolled student in Electronics or a related field at an accredited Italian university or a recent graduate (within the last 12 months) with a bachelor's or master’s degree.
- Fundamental understanding of basic electronic concepts.
- Specialized coursework in analog design or layout, acquired through your degree program, summer courses, or professional conferences, is highly valuable.
- Proficiency in understanding circuit elements such as diodes, transistors, capacitors, and resistors, as well as basic digital fundamentals like latches, flip-flops, and combinatorial logic.
- Excellent communication skills.
- Fluency in English and sufficient proficiency in Italian.
- Eligibility to work in the country of hire without restrictions.
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