South Korea Job Openings
Synopsys
Senior SoC Engineer (PI/PD)
August 4, 2024
- Responsible for Synthesis and Timing Closure at Block/Sub-system or So C level.
- Responsible for performing the input/output deliverable sanity check (Constraints analysis, LDRC, LEC, Low-Power) at the RTL/Netlist-level to enable smooth timing closure.
- Work closely with RTL design, DFT and Physical Implementation teams to meet timing closure goals.
- Play a key role in understanding the design goals to meet performance/timing requirements, understand the clocking architecture and thier relationship and lead timing related discussions at the Block/Sub-system or So C level.
Requirements :
- Experience in performing multi-mode/multi-corner timing closure of complex blocks/sub-systems or So C from synthesis to timing-signoff.
- Experience with timing constraints (SDC) development and validation at block/sub-system level for various modes.
- Ability to debug, analyze and provide solution to timing closure challenges at block/sub-system level.
- Ablity to automate or write scripts using TCL, Perl or Python.
- Understanding of Low-power concepts (UPF) and experience in performing low-power checks at the RTL/Netlist level.
- Experience in performing Logical Equivalance Checks (formal verification).
- Experience with Synopsys SDC, Fusion Compiler, Prime Time tools.
- Bachelors or Masters degree with 5+ years of experience in IC-Design/Semiconductor Engineering or related field.
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