Switzerland Job Openings

Kandou Bus

DFT Engineer CH, DE, UK

Saint-Sulpice

FULL TIME

November 12, 2024

Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy-efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.

We are actively seeking a DFT Engineer either based in Switzerland (Lausanne), Germany (Dortmund) or the UK (Northampton or Reading). In this role, you are responsible for working with multi-site teams to drive the design implementation, simulations, and to successful tape-outs.

Key Responsibilities:

Driving the DFT architectures, methodologies and tool flows for complex multi-million gate designs with Analog/high bandwidth Ser Des designs
Good understanding of ATE, Wafer bring up debug issues and drive the test engineering team for successful Silicon bring up and test program development
Define the test plan by closely working with the team and developing functional/structural tests for final/wafer test program development
Closely work with the team in defining HTOL test suite/cycle times/bring up on burn-in PCB boards
Knowledge of lab bench Silicon debug, Characterization

Qualifications:

5+ years of DFT experience including architecture specification, implementation, test pattern development, and verification
Experience with MBIST insertion, simulation, and verification on RTL and Gate Level Netlist
Experience with Scan insertion, Scan compression, Stuck-At, At-Speed test, and coverage analysis
Scan ATPG pattern generation, simulation, and debug on RTL and Gate Level Netlist
Hands-on knowledge in state-of-the-art EDA tools for DFT, design, and verification (Mentor, Cadence, Synopsys)
STA DFT Test mode timing constraint development and analysis
In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools
TCL scripting; Python scripting is a plus
Bachelor Degree minimum required in Electronics or other related fields

If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It!

Visit us at www.kandou.com and https://www.linkedin.com/company/kandou-bus-s-a-/

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