We are now looking for VLSI Physical Design Engineer (RDSS Intern) in Taiwan, Hsinchu Office. We utilize latest process technology, advanced EDA tools, and sophisticated design methodology. We always work on the most challenging designs, and push for performance limit.

What you will be doing:

• Responsible for all aspects of physical design (Netlist to GDSII & Flow development) of all chips at NVIDIA. (including Ge Force/Tegra/Tesla/Quadro)
  
• Work on floorplan(from top level to block level)
  
• Power/clock distribution
  
• Placement, routing (from top level to block level)
  
• Timing/power/noise/DFM optimization and analysis
  
• Chip assembly, and physical verification
  
• Flow automation, regression testing
  
• Work with EDA vendors on tool evaluation and improvement
  
• Develop inhouse tools and solutions
  

What we need to see:

• MS in Microelectronics, EE, CS, or related major
  
• Courses taken in IC design or digital circuit design
  
• Knowledge of chip design, Place&Route
  

Ways to stand out from the crowd:

• Project experience in IC design or ASIC design
  
• Hands-on experience in EDA tools (Place&Route, physical design, timing analysis, circuit simulation or layout)
  
• Familiar with Perl/Python/Tcl/Shell scripting
  

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.