About this vacancy

• Writing verification plans based on requirements
• Create a test plan and agree with stakeholders
• Writing IP and system level testcases
• Following up the verification team
• Issue reporting and tracking
• Completing functional verification according to the required coverage levels and schedules
• Issue reporting and tracking
• Develop and maintain test scripts to automate the verification process
• Perform verification across process corners and with post layout designs
• Assist mixed signal verification engineers
• Work with and where necessary improve existing designs
• Reporting progress and issues to the team lead/project leader and customer
• Assist with silicon validation activities

What we expect from you

• Has University Degree (Master or Bachelor) in Electrical Engineering or Electronics Engineering
• At least four years of experience in digital design and verification
• Fluent in verbal and written English
• Thorough understanding of the VHDL/Verilog/System Verilog/UVM and Cadence tools
• Ability to create and execute test plans, debug, and analyze potential issues discovered during verification
• Experience of co simulation of digital and analogue IPs to verify the whole mixed signal system
• Experience in IP and system level verification

What you can expect from us