• As an Application Engineer in the System & Verification Group (TFO-SVG) you will be responsible to provide technical support, helping Cadence customers to effectively deploy our industry leading Verification products.
• You will be in a team working with our customers to understand their needs and provide guidance on the best technologies and methodologies to enable their success, coming up with innovate solutions to address our customers’ most challenging problems.
• This role will be focused on Cadence products on the Hardware Emulation and Prototyping domain: Palladium, Protium and other tools.

• Complete Bachelor's degree in Computer/Electrical Engineering or related areas;
• Good RTL understanding and coding (Verilog, VHDL);
• Excellent English written and oral communication skills;

• Knowledge of Unix, C/C++
• Design fundamentals such as architecture, micro-architecture, HDLs Synthesis and timing
• Verification skills such as UVM testbench architecture, development and debug, System Verilog, SVA
• FPGA implementation and debug
• Fundamental So C Architecture knowledge
• Embedded software development and HW/SW co-design and co-verification
• Scripting languages (Perl, Python, TCL, Bash, etc)

• Employment category: CLT.
• Employment term: 40 hours/week.
• Competitive benefits.
• Hybrid work in Belo Horizonte, Brazil.