Brazil Job Openings
Cadence Design Systems
Lead Solutions Engineer: Digital Design - RTL and Synthesis
Belo Horizonte
FULL TIME
October 23, 2024
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Perform the digital design of So C IPs from high-level architecture to synthesis according to customer technical needs;
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Create micro-architecture specification;
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Develop RTL and System C;
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Define functional constraints and synthesize the RTL to guarantee that the design met the power, performance and area requirements;
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Support the verification and validation teams, participating in the test plan definition, coverage analysis and features debug;
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Support the physical design team to ensure that the constraints are correct and that the design is feasible to be physically implemented;
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Provide mentorship for less experienced team members.
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Complete Bachelor’s degree in Computer/Electrical Engineering or related areas;
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Strong knowledge of digital design and semiconductor fundamentals;
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Ability to design digital IPs autonomously ensuring that the IPs are delivered on time;
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Solid knowledge in designing IPs and/or integrating So Cs;
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Strong knowledge in System Verilog and/or System C;
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Solid knowledge in simulation and debug tools;
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Solid knowledge in functional constraints definition;
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Solid knowledge in logical and physical synthesis;
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Solid verbal and written skills and collaboration capabilities;
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Experience in scripting languages (Python, TCL).
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Knowledge in low power design and techniques;
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Knowledge in logical equivalence checking;
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Knowledge in clock and reset domain crossing;
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Strong knowledge in Cadence’s front-end tools (Xcelium, Verisium Debug/Simvision, Genus, Joules);
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Experience with Cadence’s physical synthesis tool (Genus and Innovus);
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Knowledge in the DFT flow.
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Employment category: CLT
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Employment term: 40 hours/week.
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Hybrid work.
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Competitive benefits.
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