• Candidate will be responsible for software development and validation of PCIe Verification IP.
• As a Lead Software Engineer, candidate is expected to participate in development efforts of the PCIe product to meet customer use model, solution requirements, protocol specification and execute necessary SW development practices to create reusable robust software solution to enable verification of these interface protocols.
• Candidate should be able to work with multi-site and diverse team. You need to effectively collaborate multi location development team to contribute in PCIe verification IP development, milestones technical roadmap and people training for success.
• The candidate is also expected work with technical support lead and key customers to resolve implementation or usage issues as Cadence VIP products are used within various verification environments and timing critical to our customer’s successes.

• Complete Bachelor's degree in Computer Science and 3+ years of experience or a related technical field with relevant 5+ years of experience.
• Extensive experience in modeling in C/C++ and background in object-oriented, algorithms, and data structures.
• In-depth understanding of complexity, analysis graph algorithms, and advanced debugging techniques for proficiency in troubleshooting software issues and debugging a large codebase.
• Strong analytical and problem-solving skills with an ability to visualize processes and outcomes.
• Outstanding all-round communication skills and ability to work collaboratively in a dynamic multi-location environment.

• Working knowledge of PCI Express (PCIe) protocol or one or more protocols USB, NVME, SATA, Display Port, etc.
• Knowledge of Verilog/System Verilog languages and OVM/UVM verification methodologies.
• Experience with digital logic design or IP/So C level Verification flow.
• Customer orientation and knowledge of the EDA tool flow.

• Employment category: CLT.
• Employment term: 40 hours/week.
• Competitive benefits.
• Hybrid work.