Israel Job Openings
Senior CPU Design Verification Engineer, Google Cloud
Tel Aviv-Yafo
FULL TIME
September 25, 2024
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
As a CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify complex digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the life-cycle of verification which can range from verification planning, test execution or collecting, and closing coverage.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
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Experience verifying digital logic at RTL level using System Verilog or Specman/E for FPGAs or ASICs.
- Experience creating and using verification components and environments in standard verification methodology.
- Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
Preferred qualifications:
-
Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
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Experience with UVM, System Verilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
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Knowledge of CPU implementation, assembly language or compute System on a Chip (So C).
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify complex digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the life-cycle of verification which can range from verification planning, test execution or collecting, and closing coverage.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
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Create and enhance constrained-random verification environments using System Verilog/UVM, or Specman.
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Identify and write all types of coverage measures for stimulus and corner-cases.
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Debug tests with design engineers to deliver functionally correct design blocks.
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Close coverage measures to identify verification holes and show progress towards tape-out.
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