Bold Tek welcomes skilled and innovative talents to join our team. With 25+ years of collective global IT service experience, we are a skilled and talented team of professionals, who live and breathe smart and innovative tech solutions to cater the needs of our global clients.
Ranging from consulting business strategy to Application Management services, that dives deep into the insights of advanced Data Science and Artificial Intelligence and further with the Digital Transformation offerings, we have built our service portfolio that delivers the overall excellence in the field of Information Technology.
We value each employee as an important asset of the organization. And we provide a good environment where our employees can learn and grow with us.
THE ROLE
The FEINT Engineer is responsible for RTL quality check, power aware synthesis, netlist check and delivery with high quality and timely. Provide the support on constrain, upf and EDA tools to design team. Provide the support on floorplan, CTS and timing closure to physical design team.
THE PERSON
You have a passion for modern, complex processor architecture, digital design, verification and implementation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES
· Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design
· Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology
· Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team
PREFERRED EXPERIENCE
· MS degree of EE, 7~10 years working experience
· Experience with Verilog RTL design/implementation and has experience of large digital ASIC project
· Experience with front-end EDA tools and flows (Fusion compiler, Prime Time, Conformal, VSI/VCLP, Formality/LEC, etc…)
· Experience with unix/linux and scripts (tcl, perl, etc.)
· Experience with physical design is a plus
· Has Synthesis or physical implement experience
· Experience with lower power design methodology
· Good English skills on talking, presentation and writing documents
· Good communication and strong sense of responsibility, task scheduling, and time management
ACADEMIC CREDENTIALS
Master’s degree in Micro Electronics/ Integrated Circuit Science, or related field preferred.
Location
Taipei, Taiwan
Business philosophy
Our Core Values:
-Integrity
-Respect
-Honesty
-Collaboration
-Courage
-Fun
-Innovation
Major goods/services
Bold Tek offers state-of-the-art technology services in areas like Application Management, Blockchain Technology, Data Management, Cloud Services, Data Science and Artificial Intelligence. It also offers IT Consulting as one of its core services along with having partnership with Smart Connect, the Intel(R) Gold Io T Solutions Partner, as a System Integrator for deploying Io T solutions, globally.
Welfare system
- Labor, health insurance, and employee group insurance
- Regular health check-ups
- A leave system that is superior to the Labor Standards Act
- Newcomers are entitled to 3 days off after 3 months of employment, plus 4 days after 6 months.
- We do not need to make up shifts on two days off per week, holidays when we see red, and make-up shifts announced by the government
- Occasional afternoon tea
- Monthly staff dinners
-Five-day work week; Saturdays and Sundays off; No make-up day
-Competitive package
-Sponsored trainings
-Opportunities to work with international team
Job Type: Full-time