Taiwan Job Openings
SiFive
Senior Design Verification Engineer
FULL TIME
October 13, 2024
The Role:
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Review and influence product definition and specifications from a verification perspective and collaborate closely with the design team on feature specifications, test plans, and failure analysis.
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Develop checkers and assertions to verify the memory subsystem designs with interconnect.
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Develop tools, test benches, and test suites (UVM, C++/C, or otherwise as needed) to execute test plans.
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Develop and maintain an in-house Verification IP (VIP) tailored for memory subsystem and interconnect testing
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Write functional coverage, analyze both code and functional coverage, and close coverage holes.
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At least 3+ years of recent experience with standard verification tools and methodologies (System Verilog/UVM, Verdi/DVE, Verilog, Makefiles, scripting languages, etc.).
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Familiarity with the AMBA protocol is a plus.
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Solid understanding of processor and So C architecture, or a strong desire and ability to learn the same.
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A thorough understanding of the high-level verification flow methodology (test plan generation, test generation, failure analysis, coverage analysis and closure).
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Proficient in troubleshooting and possessing strong analytical capabilities.
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Good interpersonal skills to listen to diverse points of view and influence people from different disciplines.
Benefits
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