Israel Job Openings
Junior SoC Design Verification Engineer, Google Cloud
Tel Aviv-Yafo
FULL TIME
August 27, 2024
Minimum qualifications:
-
Bachelor's degree in Electrical Engineering, Computer Engineering, a related technical field of study, or equivalent practical experience.
-
Experience creating and using verification components and environments in standard verification methodology.
- Experience verifying digital logic at RTL level using System Verilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs.
Preferred qualifications:
-
Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
About the job
As a Junior So C Design Verification Engineer, you will work as part of a Research and Development team, and will build verification components, constrain random testing, system testing, and verification closure. As part of our server chip design team, you will use your design and verification expertise to verify complex digital designs. You will collaborate closely with design and verification engineers in active projects and perform verification. You'll build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. In addition, you will be responsible for the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using System Verilog and UVM, or formally verify designs with SVA and industry leading formal tools.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
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