Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
  
• Experience in RTL2GDS, Static Timing Analysis (STA) flows, and methodologies.
  
• Experience with physical design tools (e.g., Synopsys, Cadence) and timing signoff (Primetime).
  
• Experience with Static Timing Analysis, sign-off corner definitions, process margining, SDC development, high frequency convergence, and setting up frequency goals with technology scaling.

Preferred qualifications:

• Experience with Alternating Current (AC) timing from specs to implementation.
  
• Experience with Cpp Defensive Coding (CDC) design and CDC constraints.
  
• Experience in Application-Specific Integrated Circuit (ASIC) physical design, physical design flows and methodologies, synthesis, place and route, and formal verification.
  
• Knowledge of Design for testing (DFT) modes, noise and signal integrity effects.
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.