Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Chemical Engineering, Physics, Chemistry, Material Science, a related field, or equivalent practical experience.
  
• 4 years of experience in ASIC physical design flows and methodologies in advanced process nodes.
  
• 3 years of experience in software development, or 1 year of experience with an advanced degree.
  
• Experience with one or more synthesis/Pn R tools (e.g., Genus, Innovus, DC, ICC).
• Experience in high-performance synthesis, Pn R, sign-off convergence, including STA and sign-off optimizations.

Preferred qualifications:

• Experience in low power design Implementation including Common Power Format (CPF)/Unified Power Format (UPF), multi-voltage domains, power gating.
• Experience in floor planning and block integration.
  
• Experience with ASIC design flows and methodology of Physical design.
  
• Experience in engineering across physical design, top-level implementation, GDS tape-out.
  
• Understanding of Circuit design, device physics and deep submicron technology.
  
• Excellent skills in scripting languages such as Python, Tcl, or Perl.
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.