The Barcelona Supercomputing Center - Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain. It houses Mare Nostrum, one of the most powerful supercomputers in Europe, was a founding and hosting member of the former European HPC infrastructure PRACE (Partnership for Advanced Computing in Europe), and is now hosting entity for Euro HPC JU, the Joint Undertaking that leads large-scale investments and HPC provision in Europe. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress. BSC combines HPC service provision and R&D into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over 1000 staff from 60 countries.

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We are particularly interested for this role in the strengths and lived experiences of women and underrepresented groups to help us avoid perpetuating biases and oversights in science and IT research. In instances of equal merit, the incorporation of the under-represented sex will be favoured.

We promote Equity, Diversity and Inclusion, fostering an environment where each and every one of us is appreciated for who we are, regardless of our differences.

If you consider that you do not meet all the requirements, we encourage you to continue applying for the job offer. We value diversity of experiences and skills, and you could bring unique perspectives to our team.

The Barcelona Supercomputing Center (BSC) www.bsc.es is embarking on an umbrella of large-scale projects to design, and manufacture an open-source High Performance Out-of-Order Vector Processing Unit that will serve as the basic building block of BSCs next generation supercomputer, the Marenostrum 6 (MN6) which will be operational in 2028/2029. In this ambitious and potentially rewarding endeavor, we need engineers and computer scientists at all levels of expertise (from 0 to 20+ years) and in both hardware and software fields. The final team will be 100 engineers and scientists.
The applicants would ideally have experience/ambition in at least one or more of the following fields:

• Hardware (Processor architecture, micro-architecture, accelerators, memory hierarchy, memory controllers, HBM, DRAM, non-volatile memory, RTL design, VHDL, verilog, System C, System verilog, Synopsys, Cadence, Mentor Graphics, synthesis, place and route, timing closure, packaging, PCB design, verification, validation, CI, post-silicon debug, DFT, gate-level simulation)

• Software (programming models, MPI, compilers, operating systems, managed runtimes, Open MP, task-based programming models, containers, security, fault-tolerance, virtualization C/C++, Tcl, Python, Perl/Csh )