Malaysia Job Openings
SAGCLAY
FPGA / RTL Design Engineer
October 11, 2024
Location: Penang, Malaysia
Experience: 5+ years
Availability: 30 days
Job Overview:
As an FPGA/RTL Design Engineer, you will be responsible for FPGA design, RTL coding, and functional verification using System Verilog. Your work will involve creating test benches for verification and integrating designs into Intel FPGAs for testing new platforms.
Key Responsibilities:
- Design and implement FPGA solutions using RTL coding
- Perform functional verification using System Verilog
- Construct test benches for comprehensive functional verification
- Load designs onto Intel FPGAs and conduct functional tests for new Intel platforms
- 5+ years of FPGA design experience
- 6+ years of experience with RTL design (Verilog, System Verilog, VHDL)
- Familiarity with the complete design cycle of large FPGAs, from RTL to functional verification
- Preferably experienced with Intel FPGAs
- Proficiency in Perl and C
- Expertise with tools like Synplify, VCS, Modelsim, and Intel ISE
- Knowledge of THC, USB2, microprocessor, e SPI, and audio at RTL level is a plus
- Strong understanding of RTL coding and functional verification
Contract length: 12 months
Pay: RM7,000.00 - RM9,000.00 per month
Benefits:
- Health insurance
- Day shift
- RTL coding: 5 years (Preferred)
- Intel FPGAs and Synplify tools: 1 year (Preferred)
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