Overview: Responsibilities:

• Verification of Analog/HSIO DFx architecture and features
• Build testbench components to support the next generation of NBIO IPs
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Develop, maintain and improve test libraries to support IP level testing
• Test coverage and test cost reduction analysis
• Provide technical support to So C and Post-Si teams to ensure successful bring up and enhance yield learning

• Understanding of Design for Test methodologies and DFT verification experience (e.g. JTAG 1149.x, Scan, Memory BIST, PRBS, IO Loopback, etc.)
• Understanding of Design for Debug methodologies and DFD features verification experience (e.g., Debug bus, Tracing, Trigger, Logic Analyzer, etc.)
• Experienced with Verilog, System Verilog, C, and C++
• Developing UVM based verification frameworks and testbenches, processes and flows
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
• Debug test failures to determine the root cause; work with design engineers to resolve design defects and correct any test issues
• Experience with ATE (Automatic Test Equipment) - ATE test pattern & test flow development, debug, test and characterization
• Experience in post-Si system level debug and use of tools such as JTAG debuggers, logic analyzers, and PCIe bus analyzers

• Bachelor’s or master’s degree in related discipline preferred

Qualifications: