Overview: Responsibilities:

• Layout of basic digital and analog building blocks using analog transistor level components.
• Layout of analog macros, power pads, and input/output pads using above blocks
• Working closely with Analog designers in floorplanning; power grid and signal flow planning
• Physical and electrical verification include DRC, LVS, EM/IR, ERC, PERC Latch up and PERC ESD
• Creation of blackbox models for other groups in the design flow

• Must have detailed knowledge of CMOS circuit theory.
• Must have ability to communicate with various teams to articulate specs and requirements as they pertain to layout
• Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools
• Must have at least 5 years of relevant or comparable experience doing analog layout design
• Knowledge of chip level integration and ESD concepts a plus
• Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability
• Good understanding of signal and clock shielding and isolation techniques
• Ability to work well as part of a team

• Bachelor’s degree in Engineering (or related field) OR Associates Degree in Engineering.

Qualifications: