Overview: Responsibilities:

• Collaborating with architects and designers to understand the design intents.
• Creating and executing formal verification plans for design blocks.
• Writing and debugging properties to verify the design, analyzing signatures and pushing for the resolution.
• Optimizing runtime using formal techniques.
• Collecting and reporting status and progress.
• Improving formal setups based on feedbacks from reviews, metrics, etc.
• For senior level positions:
• • Leading and coordinating verification activities for a small team.
  • Training and couching junior engineers.
  • Developing working procedures, flows and infra.
  • Handling complicated formal problems.

• 5+ years of combined ASIC/FPGA design and verification experience.
• Strong background in formal property verification (FPV), sequential equivalence checking (SEC/SEQ/SLEC), and/or academic formal methods.
• Expertise in a formal property language (SVA preferred), abstraction techniques, formal sign-off and commercial formal tools (VC-Formal, Jasper Gold, Questa Formal, etc.).
• Extensive experience verifying complex, packet or control based designs.
• Familiarity with industry standard high-speed protocols such as PCIe, CXL, SATA, USB, AXI, UCIe, etc.
• Experience with verification of Hardware-Firmware interaction is highly desirable.

• BS (or higher) degree in Electronics/Electrical or Computer Engineering desired.

Qualifications: