Overview: Responsibilities:
KEY RESPONSIBLITIES:

• Able to work well inside team/cross functional team.
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
• Estimate the time required to write the new feature tests and any required changes to the test environment.
• Build the directed and random verification tests.
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues .
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.

• Experience in IP level ASIC verification.
• Experience in debugging firmware and RTL code using simulation tools.
• Experience in using UVM testbenches and working in Linux and Windows environments.
• Good understanding with UVM, Verilog, System Verilog, C, and C++
• USB,UFS,Ethernet,PCIE,AXI knowledge is a plus
• Good understanding and hands-on experience in the UVM concepts and System Verilog language. (SVA, UVM scoreboard)
• Good working knowledge of System C and TLM with some related experience.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Over 5 yrs of digital IP verification with SV/UVM/formal verification or new methodology of the industry

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering.

LOCATION:
Penang, Malaysia


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Qualifications: