Overview: Responsibilities:
THE ROLE:

• Physical design including block level place/cts/route, full chip floor planning, timing closure, physical verification etc.

THE PERSON:

• Always be positive, dedicated and good team player
• Good listening, writing, and speaking English
• Good communication skills

KEY RESPONSIBILITIES:

• Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation.
• Focus on physical design of deep sub-micron GPU chips including block level, full chip floor planning, timing closure, place and route, physical verification etc.
• The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team.
• The individual is also expected to be accountable for project delivery.

PREFERRED EXPERIENCE:

• Tape-out experience in deep submicron process
• Knowledgeable in all aspects of ASIC design flow
• Demonstrate strong leadership and work well with cross-functional teams
• Demonstrate strong leadership, work well with cross-functional teams
• Familiar with Unix/Linux environment
• Familiar with Back-End (physical design) EDA tools
• Familiar with Front-End EDA tools
• Good at scripts, like Python/perl/Tcl/shell

ACADEMIC CREDENTIALS:

• MSEE / Microelectronic preferred
• MSEE with 15+ years or Bachelor with 18+ years of industrial experience in ASIC design

Qualifications: